In video system applications, a picture is displayed on a television or a computer screen by scanning an electrical signal horizontally across the screen one line at a time using a scanning circuit. The amplitude of the signal at any one point on the line represents the brightness level at that point on the screen. When a horizontal line scan is completed, the scanning circuit is notified to retrace to the left edge of the screen and start scanning the next line provided by the electrical signal. Starting at the top of the screen, all the lines to be displayed are scanned by the scanning circuit in this manner. A frame contains all the elements of a picture. The frame contains the information of the lines that make up the image or picture and the associated synchronization signals that allow the scanning circuit to trace the lines from left to right and from top to bottom.
There may be two different types of picture or image scanning in a video system. For some television signals, the scanning may be interlaced video format, while for some computer signals the scanning may be progressive or non-interlaced video format Interlaced video occurs when each frame is divided into two separate sub-pictures or fields. These fields may have originated at the same time or at subsequent time instances. A field may be a top field type or a bottom field type based on whether it comprises the first horizontal line or the second horizontal line of a video frame. The interlaced picture may be produced by first scanning the horizontal lines for the first field and then retracing to the top of the screen and then scanning the horizontal lines for the second field. The progressive, or non-interlaced, video format may be produced by scanning all of the horizontal lines of a frame in one pass from top to bottom.
There has been for many years problems associated with supporting both interlaced content and interlaced displays along with progressive content and progressive displays. Many advanced video systems support either one format or the other format. As a result, deinterlacers, devices or systems that convert interlaced video format into progressive video format, became an important component in many video systems.
However, the design and implementation of deinterlacers in integrated circuits (ICs) may be very complex since many different subsystems are necessary to perform and/or control the operations that convert interlaced video format into progressive video format. As a result, the operation and/or functionality of the many different subsystems that comprise these complex architectures may be very difficult to verify during the design phase. Moreover, the operation and/or functionality of deinterlacers may dynamically change since the contents of a video field stream may be changing with time. This difficulty persists whether benchtests generated for verification are developed for deinterlacer hardware models based on a Register Transfer Level (RTL) description or on representations based on hardware description languages (HDLs) such as Verilog or VHDL. For example, hundreds or even thousands of video fields may be necessary to verify a portion of the operations in a specific hardware implementation of a deinterlacer. In this regard, finding and isolating design flaws may be very time consuming and may lead to either an incomplete verification of a deinterlacer system or to a prolonged verification period which may adversely affect the time to market of a product.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.